module port_selector (
    output      WE_s,   
    output      RE_s,   
    output      CLE,   
    output      ALE,  

    input[7:0]  DQ_i,
    output[7:0] DQ_o, 
    output      DQ_oen, 

    input       DQS_i,
    output      DQS_o,
    output      DQS_oen, 

/***********Mode control port**************/
    input[3:0]  portMode,
    input       clkX2,
    input       dclk,
    input       rst_n,
    input[2:0]  Cmd,  //
    input[7:0]  InputVal,       //
    output      IV_En,
    output[7:0] ReadVal,
    output      RV_En,
    input[31:0] RWDataNum,
    input[31:0] RWDataCounter
);
  


/*********************** toggle mode port **************************/
wire        tog_we_s_w;//portMode[0]
wire        tog_re_s_w;
wire        tog_cle_w;
wire        tog_ale_w;
wire[7:0]   tog_dq_i_w;
wire[7:0]   tog_dq_o_w;
wire        tog_dq_oen_w;
wire        tog_dqs_i_w;
wire        tog_dqs_o_w;
wire        tog_dqs_oen_w;
wire[2:0]   tog_port_cmd_reg;
wire[7:0]   tog_port_data_in_reg;
wire        tog_port_data_in_en;
wire[7:0]   tog_port_data_out_reg;
wire        tog_port_data_out_vaild;
wire[31:0]  tog_port_data_number;
wire[31:0]  tog_port_data_counter;

Toggle_port u_Toggle_port(
	.WE_s          (tog_we_s_w      ),
    .RE_s          (tog_re_s_w      ),
    .CLE           (tog_cle_w       ),
    .ALE           (tog_ale_w       ),
    .DQ_i          (tog_dq_i_w      ),
    .DQ_o          (tog_dq_o_w      ),
    .DQ_oen        (tog_dq_oen_w    ),
    .DQS_i         (tog_dqs_i_w     ),
    .DQS_o         (tog_dqs_o_w     ),
    .DQS_oen       (tog_dqs_oen_w   ),

    .clkX2         (clkX2         ),
    .dclk          (dclk      ),
    .rst_n         (rst_n       ),

    .Cmd           (tog_port_cmd_reg          ),
    .InputVal      (tog_port_data_in_reg      ),
    .IV_En         (tog_port_data_in_en       ),
    .ReadVal       (tog_port_data_out_reg     ),
    .RV_En         (tog_port_data_out_vaild   ),
    .RWDataNum     (tog_port_data_number      ),
    .RWDataCounter (tog_port_data_counter     )
);


/*********************** async mode cycle **************************/
wire        sdr_we_s_w;//portMode[1]
wire        sdr_re_s_w;
wire        sdr_cle_w;
wire        sdr_ale_w;
wire[7:0]   sdr_dq_i_w;
wire[7:0]   sdr_dq_o_w;
wire        sdr_dq_oen_w;

wire[2:0]   sdr_port_cmd_reg;
wire[7:0]   sdr_port_data_in_reg;
wire        sdr_port_data_in_en;
wire[7:0]   sdr_port_data_out_reg;
wire        sdr_port_data_out_vaild;

Async_port u_Async_port(
	.WE_s          (sdr_we_s_w          ),
    .RE_s          (sdr_re_s_w          ),
    .CLE           (sdr_cle_w           ),
    .ALE           (sdr_ale_w           ),
    .DQ_i          (sdr_dq_i_w          ),
    .DQ_o          (sdr_dq_o_w          ),
    .DQ_oen        (sdr_dq_oen_w        ),

    .clkX2         (clkX2                 ),
    .dclk          (dclk              ),
    .rst_n         (rst_n               ),

    .Cmd           (sdr_port_cmd_reg        ),
    .InputVal      (sdr_port_data_in_reg    ),
    .IV_En         (sdr_port_data_in_en     ),
    .ReadVal       (sdr_port_data_out_reg   ),
    .RV_En         (sdr_port_data_out_vaild )
);

/*********************** sync mode cycle **************************/
wire        syn_we_s_w;//portMode[2]
wire        syn_re_s_w;
wire        syn_cle_w;
wire        syn_ale_w;
wire[7:0]   syn_dq_i_w;
wire[7:0]   syn_dq_o_w;
wire        syn_dq_oen_w;
wire        syn_dqs_i_w;
wire        syn_dqs_o_w;
wire        syn_dqs_oen_w;
wire[2:0]   syn_port_cmd_reg;
wire[7:0]   syn_port_data_in_reg;
wire        syn_port_data_in_en;
wire[7:0]   syn_port_data_out_reg;
wire        syn_port_data_out_vaild;
wire[31:0]  syn_port_data_number;
wire[31:0]  syn_port_data_counter;

Sync_port u_Sync_port(
	.CLK           (syn_we_s_w      ),
    .WR            (syn_re_s_w      ),
    .CLE           (syn_cle_w       ),
    .ALE           (syn_ale_w       ),
    .DQ_i          (syn_dq_i_w      ),
    .DQ_o          (syn_dq_o_w      ),
    .DQ_oen        (syn_dq_oen_w    ),
    .DQS_i         (syn_dqs_i_w     ),
    .DQS_o         (syn_dqs_o_w     ),
    .DQS_oen       (syn_dqs_oen_w   ),

    .clkX2         (clkX2                 ),
    .dclk          (dclk              ),
    .rst_n         (rst_n               ),
    
    .Cmd           (syn_port_cmd_reg        ),
    .InputVal      (syn_port_data_in_reg    ),
    .IV_En         (syn_port_data_in_en     ),
    .ReadVal       (syn_port_data_out_reg   ),
    .RV_En         (syn_port_data_out_vaild ),
    .RWDataNum     (syn_port_data_number    ),
    .RWDataCounter (syn_port_data_counter   )
);
/*********************** nvddr2 mode cycle **************************/

wire        ddr_we_s_w;//portMode[3]
wire        ddr_re_s_w;
wire        ddr_cle_w;
wire        ddr_ale_w;
wire[7:0]   ddr_dq_i_w;
wire[7:0]   ddr_dq_o_w;
wire        ddr_dq_oen_w;
wire        ddr_dqs_i_w;
wire        ddr_dqs_o_w;
wire        ddr_dqs_oen_w;
wire[2:0]   ddr_port_cmd_reg;
wire[7:0]   ddr_port_data_in_reg;
wire        ddr_port_data_in_en;
wire[7:0]   ddr_port_data_out_reg;
wire        ddr_port_data_out_vaild;
wire[31:0]  ddr_port_data_number;
wire[31:0]  ddr_port_data_counter;

ddr2_port u_ddr2_port(
	.WE_s          (ddr_we_s_w      ),
    .RE_dif        (ddr_re_s_w      ),
    .CLE           (ddr_cle_w       ),
    .ALE           (ddr_ale_w       ),
    .DQ_i          (ddr_dq_i_w      ),
    .DQ_o          (ddr_dq_o_w      ),
    .DQ_oen        (ddr_dq_oen_w    ),
    .DQS_i         (ddr_dqs_i_w     ),
    .DQS_o         (ddr_dqs_o_w     ),
    .DQS_oen       (ddr_dqs_oen_w   ),

    .clkX2         (clkX2              ),
    .dclk          (dclk               ),
    .rst_n         (rst_n              ),

    .Cmd           (ddr_port_cmd_reg         ),
    .InputVal      (ddr_port_data_in_reg     ),
    .IV_En         (ddr_port_data_in_en      ),
    .ReadVal       (ddr_port_data_out_reg    ),
    .RV_En         (ddr_port_data_out_vaild  ),
    .RWDataNum     (ddr_port_data_number     ),
    .RWDataCounter (ddr_port_data_counter    )
);

data_sel #(1)u0_data_sel(portMode, WE_s, tog_we_s_w, sdr_we_s_w, syn_we_s_w, ddr_we_s_w);
data_sel #(1)u1_data_sel(portMode, RE_s, tog_re_s_w, sdr_re_s_w, syn_re_s_w, ddr_re_s_w);
data_sel #(1)u2_data_sel(portMode, CLE,  tog_cle_w,  sdr_cle_w,  syn_cle_w,  ddr_cle_w);
data_sel #(1)u3_data_sel(portMode, ALE,  tog_ale_w,  sdr_ale_w,  syn_ale_w,  ddr_ale_w);
data_sel #(8)u4_data_sel(portMode, DQ_o,     tog_dq_o_w,              sdr_dq_o_w,              syn_dq_o_w,              ddr_dq_o_w);
data_sel #(1)u5_data_sel(portMode, DQ_oen,   tog_dq_oen_w,            sdr_dq_oen_w,            syn_dq_oen_w,            ddr_dq_oen_w);
data_sel #(1)u6_data_sel(portMode, DQS_o,    tog_dqs_o_w,             ,                        syn_dqs_o_w,             ddr_dqs_o_w);
data_sel #(1)u7_data_sel(portMode, DQS_oen,  tog_dqs_oen_w,           ,                        syn_dqs_oen_w,           ddr_dqs_oen_w);
data_sel #(1)u8_data_sel(portMode, IV_En,    tog_port_data_in_en,     sdr_port_data_in_en,     syn_port_data_in_en,     ddr_port_data_in_en);
data_sel #(1)u9_data_sel(portMode, RV_En,    tog_port_data_out_vaild, sdr_port_data_out_vaild, syn_port_data_out_vaild, ddr_port_data_out_vaild);
data_sel #(8)ua_data_sel(portMode, ReadVal,  tog_port_data_out_reg,   sdr_port_data_out_reg,   syn_port_data_out_reg,   ddr_port_data_out_reg);
data_sel_in #(8)u1_data_sel_in(portMode,  DQ_i,          tog_dq_i_w,             sdr_dq_i_w,             syn_dq_i_w,             ddr_dq_i_w);
data_sel_in #(1)u2_data_sel_in(portMode,  DQS_i,         tog_dqs_i_w,            ,                       syn_dqs_i_w,            ddr_dqs_i_w);
data_sel_in #(3)u3_data_sel_in(portMode,  Cmd,           tog_port_cmd_reg,       sdr_port_cmd_reg,       syn_port_cmd_reg,       ddr_port_cmd_reg);
data_sel_in #(8)u4_data_sel_in(portMode,  InputVal,      tog_port_data_in_reg,   sdr_port_data_in_reg,   syn_port_data_in_reg,   ddr_port_data_in_reg);
data_sel_in #(32)u5_data_sel_in(portMode, RWDataNum,     tog_port_data_number,   ,                       syn_port_data_number,   ddr_port_data_number);
data_sel_in #(32)u6_data_sel_in(portMode, RWDataCounter, tog_port_data_counter,  ,                       syn_port_data_counter,  ddr_port_data_counter);

endmodule